1. Field of the Invention
This invention relates to a semiconductor system, a connection test method of the semiconductor system, and a manufacturing method of the semiconductor system and more particularly to a fault tolerant semiconductor system and a fault correction technique for compensating for poor connection of a wiring between a plurality of semiconductor: chips, a semiconductor chip and a wiring board or a semiconductor chip and a TAB tape in a semiconductor system having a plurality of semiconductor chips contained in one package.
2. Description of the Related Art
In order to realize data processing with broad band width, it is effective to use a semiconductor system (module) having a plurality of semiconductor chips contained in one package. In the above semiconductor system, it is necessary to make a function test of each semiconductor chip and a connection test between the semiconductor chips after electrical connection between the semiconductor chips is made by use of the flip chip technique, for example.
In this type of semiconductor system, the semiconductor chips are divided into a semiconductor chip (which is hereinafter referred to as a parent chip) having an external I/O and a semiconductor chip (which is hereinafter referred to as a child chip) having no external I/O.
FIG. 1 shows one example of a semiconductor system in which a parent chip 100 and a child chip 200 are arranged with respective main surfaces (element forming surfaces) 100a, 200a thereof set to face each other and electrodes formed on the element forming surfaces 100a, 200a of the chips are electrically connected to each other via wirings (bumps) 300.
In the semiconductor system with the above configuration, it is impossible to directly supply a test signal from the exterior to the child chip 200 having no external I/O. Therefore, a circuit used to transmit/receive a test signal between the parent chip 100 and the child chip 200 and a wiring used to transfer the test signal between the chips are provided.
Conventionally, in the above semiconductor system, a product which is determined to contain poor connection (or connection failure) as the result of the test for connection between the chips is dealt with as a defective product (fail). However, if the semiconductor product is further systemized in future and the number of semiconductor chips and the number of wirings between the chips are increased accordingly, the possibility that poor connection between the chips will occur becomes stronger. Therefore, there occurs a possibility that the manufacturing yield of the products is lowered due to poor connection between the chips and it is desired to take effective measures.